1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, relates to a technique for booting a semiconductor device using a boot program stored in a nonvolatile memory.
2. Description of the Related Art
In recent years, system LSIs (large scale integrated circuits), which integrate various functions on a single chip, are designed to store various processing programs and data, such as a boot program, in an externally- or internally-provided non-volatile memory. As such a nonvolatile memory, a flash memory, which electrically rewrites and erases data, is often used.
Generally, NOR type flash memories are used for storing boot programs; however, NAND type flash memories, which are advantageous in the light of the cost, are also used for this purpose in recent days. One issue is that NAND type flash memories may suffer from an increased number of accidental defects due to manufacture, compared with NOR type flash memories. When a system LSI is booted with a boot program stored in an NAND type flash memory, it is required to assure that the block storing the boot program is not a failure block and the boot program is normally stored.
Data accesses to an NAND type flash memory are sequentially executed. Specifically, an access to an NAND type flash memory begins with specifying addresses for respective desired access cycles after entering a predefined command. This is followed by writing and/or reading data from or into pages corresponding to the specified addresses. Each specified address indicates the starting address of the corresponding page, and read and write operation of data are executed in units of pages. When a boot program is stored within multiple pages, a plurality of addresses are sequentially specified, and program data of the boot program stored in the plurality of pages are sequentially read out from the corresponding pages.
Disadvantageously, NAND-type flash memories suffer from increased bit errors, compared to NOR-type flash memories. First, NAND type flash memories tend to suffer from an increased number of manufacture defects. Second, in a NAND type flash memory, a set of memory cells are serially connected and this may result in that a failure memory cell causes a bit error of another memory cell. Bit lines of an NAND type flash memory are formed of serially-connected drains and sources of memory cells; no dedicated metal bit lines are provided within a memory array of an NAND type flash memory. Although effectively improving the cell size and integration degree, such structure undesirably increases the bit error rate. An NOR type flash memory, on the other hand, includes bitlines provided separately from memory cells for reading values of the memory cells. Such structure avoids a memory cell being affected by the state of another memory cell.
Therefore, WAND type flash memories often employ an error correction code (ECC) for reducing bit errors. The hamming code technique, which is used in smart mediums, is one simple example of the ECC technique. The use of the (7, 4) hamming code allows correcting one bit error, and detecting two random bit errors. In general, the error detection and correction by using the ECC technique is executed on dedicated hardware, such as an ECC circuit.
Japanese Laid-Open Patent Application No. Jp-A 2005-215824 (hereinafter, referred to as the '824 application) discloses a technique for booting a system LSI by using an NAND type flash memory. In this technique, the NAND type flash memory stores the same boot programs in multiple blocks. When an error is founded in the boot program read from a certain block, the boot program is read again from the starting page of another block. This allows stable booting, even when the NAND type flash memory includes one or more defective blocks.
More specifically, the system LSI disclosed in the '824 application includes a CPU that specifies a read address of a flash memory and a flash memory controller that obtains data from the specified read address of the flash memory. In the flash memory, the same boot programs are stored in multiple blocks. When the boot program is read out from a certain block, an ECC circuit in the flash memory controller performs error detection and correction for the boot program read out. When an error is detected, the read address is modified to reselect another block by an readdressing circuit. The flash memory controller obtains the boot program from the starting address of the reselected block, and transfers the obtained boot program to the CPU.
The drawback of this technique, which avoids bit errors in units of blocks, is that the boot program is not successfully read out when all of the respective blocks include a defective page, which results in undesirable termination of the booting process.
The following is a detailed description of this drawback for a case where the same boot programs are stored in first to third blocks each composed of 0th to 31st pages. When the ECC circuit finds an error in the data read from, for example, the 5th page of the first block, the readdressing circuit modifies the read address to specify the starting address of the 0th page of the second block. The flash memory controller reads the boot program from the second block in the order from the 0th page to the 31th page in accordance with the modified read address. When the ECC circuit finds another error in the data read from, for example, the 10th page of the second block, the readdressing circuit modifies the read address to specify the 0th page of the third block. In the same way, the flash memory controller finally reads the boot program from the third block in the order from the 0th page to the 31th page in accordance with the modified read address. When another error is found in the data read from the third block, however, this process results in that the boot program is not successfully read out from the flash memory.